老师给看一下吧,画的难看,错误无数,要交智商税了.

vanday · 发表于 2018-4-19 19:25:47

*PADS-ECO-V10.0-MILS*
*REMARK*  old file: D:\study\电路设计\逆天PCB 4月班\第四期视频\www.NTpcb.com-1元学习PADS-第4期-项目1上课资料\校验原理图的文件\GL850G_asc.asc
*REMARK*  new file: C:\PADS Projects\ecogtmp1.asc
*REMARK*  created by ECOGEN (Version 6.4v) on 2018/4/19 19:23:37

PART DIFFERENCES
----------------
OLD DESIGN                                     NEW DESIGN
Ref-des Part-type

ecal Ref-des Part-type

ecal
EC1 C0805                                     EC1 C0603
EC5 C0805                                     EC5 C0603
EC2 CED-6_3-2_5                               EC2 CED-6_3_2_5
EC3 CED-6_3-2_5                               EC3 CED-6_3_2_5
EC4 CED-6_3-2_5                               EC4 CED-6_3_2_5
EC6 CED-6_3-2_5                               EC6 CED-6_3_2_5

NET DIFFERENCES
----------------
OLD DESIGN                                     NEW DESIGN
DGND                                           GND
N15274073                                        $$$53
N15275140                                        $$$3109
N15275302                                        $$$1093
N15275414                                        $$$3105
N15278057                                        $$$2074
N15278073                                        $$$3098
N15289456                                        $$$30317

SWAPPED GATE DIFFERENCES
------------------------
OLD DESIGN                                     NEW DESIGN

SWAPPED PIN DIFFERENCES
------------------------
OLD DESIGN                                     NEW DESIGN

UNMATCHED NET PINS IN OLD DESIGN
--------------------------------
DGND             EC5.2
DM1                DOWN1.2 U1.27
DM2                DOWN2.2 U1.2
DM3                DOWN3.2 U1.8
DP1                U1.28 DOWN1.3
DP2                DOWN2.3 U1.3
DP3                DOWN3.3 U1.9
VCC                EC5.1 F1.2
VCC_USB          F1.1

UNMATCHED NET PINS IN NEW DESIGN
--------------------------------
DGND             C6.1 C1.1 C2.1 C3.1 C4.1 C5.1
                  R7.1 R3.1 C8.1 C9.1 C10.1 R5.1 U1.15
                  EC1.2 J1.2 UP1.5 UP1.G1 DOWN4.G1 DOWN3.G1 DOWN2.G1
                  DOWN1.G1 UP1.G2 DOWN4.G2 DOWN3.G2 DOWN2.G2 DOWN1.G2 UP1.G3
                  UP1.G4
DM1                U1.27
DM2                U1.2
DM3                U1.8
DM4                DOWN3.2 DOWN2.2 DOWN1.2
DP1                U1.28
DP2                U1.3
DP3                U1.9
DP4                DOWN3.3 DOWN2.3 DOWN1.3
VCC                F1.1 EC5.2
VCC_USB          F1.2

ATTRIBUTE DIFFERENCES
---------------------
Attribute Level [ OLD DESIGN Parent -> NEW DESIGN Parent ]

      Attribute Name          Old Value             New Value
PART C6 -> C6
      Value                   <no attr>             0.1uF

RULES DIFFERENCES (Values in mils)
-----------------
Object Type Object Name [ OLD DESIGN -> NEW DESIGN ] Rule Type

      Rule Name             Old Value             New Value

DEFAULT       CLEARANCE
      TRACK_TO_TRACK          <no rule>             6.000000
      VIA_TO_TRACK          <no rule>             6.000000
      VIA_TO_VIA             <no rule>             6.000000
      PAD_TO_TRACK          <no rule>             6.000000
      PAD_TO_VIA             <no rule>             6.000000
      PAD_TO_PAD             <no rule>             6.000000
      SMD_TO_TRACK          <no rule>             6.000000
      SMD_TO_VIA             <no rule>             6.000000
      SMD_TO_PAD             <no rule>             6.000000
      SMD_TO_SMD             <no rule>             6.000000
      COPPER_TO_TRACK       <no rule>             6.000000
      COPPER_TO_VIA          <no rule>             6.000000
      COPPER_TO_PAD          <no rule>             6.000000
      COPPER_TO_SMD          <no rule>             6.000000
      COPPER_TO_COPPER       <no rule>             6.000000
      TEXT_TO_TRACK          <no rule>             6.000000
      TEXT_TO_VIA             <no rule>             6.000000
      TEXT_TO_PAD             <no rule>             6.000000
      TEXT_TO_SMD             <no rule>             6.000000
      OUTLINE_TO_TRACK       <no rule>             6.000000
      OUTLINE_TO_VIA          <no rule>             6.000000
      OUTLINE_TO_PAD          <no rule>             6.000000
      OUTLINE_TO_SMD          <no rule>             6.000000
      OUTLINE_TO_COPPER       <no rule>             6.000000
      DRILL_TO_TRACK          <no rule>             6.000000
      DRILL_TO_VIA          <no rule>             6.000000
      DRILL_TO_PAD          <no rule>             6.000000
      DRILL_TO_SMD          <no rule>             6.000000
      DRILL_TO_COPPER       <no rule>             6.000000
      SAME_NET_SMD_TO_VIA    <no rule>             6.000000
      SAME_NET_SMD_TO_CRN    <no rule>             6.000000
      SAME_NET_VIA_TO_VIA    <no rule>             6.000000
      SAME_NET_PAD_TO_CRN    <no rule>             6.000000
      MIN_TRACK_WIDTH       <no rule>             6.000000
      REC_TRACK_WIDTH       <no rule>             6.000000
      MAX_TRACK_WIDTH       <no rule>             6.000000
      DRILL_TO_DRILL          <no rule>             6.000000
      BODY_TO_BODY          <no rule>             6.000000
      SAME_NET_TRACK_TO_CRN <no rule>             6.000000

DEFAULT       ROUTING
      LENGTH_MINIMIZATION_TYPE <no rule>             TOTAL
      TRACE_SHARE             <no rule>             ON
      VIA_SHARE             <no rule>             ON
      AUTO_ROUTE             <no rule>             ON
      RIPUP                   <no rule>             ON
      SHOVE                   <no rule>             ON
      ROUTE_PRIORITY          <no rule>             3
      MAX_NUMBER_OF_VIAS    <no rule>             -1
      VALID_LAYER             <no rule>             顶面
      VALID_LAYER             <no rule>             底面
      VALID_VIA_TYPE          <no rule>             *USE_CURRENT*
      SHOVE_PROTECTED       <no rule>             OFF

DEFAULT       HIGH_SPEED
      MIN_LENGTH             <no rule>             0.000000
      MAX_LENGTH             <no rule>             50000.000000
      STUB_LENGTH             <no rule>             0.000000
      PARALLEL_LENGTH       <no rule>             1000.000000
      PARALLEL_GAP          <no rule>             200.000000
      TANDEM_LENGTH          <no rule>             1000.000000
      TANDEM_GAP             <no rule>             200.000000
      MIN_DELAY             <no rule>             0.000000
      MAX_DELAY             <no rule>             10.000000
      MIN_CAPACITANCE       <no rule>             0.000000
      MAX_CAPACITANCE       <no rule>             10.000000
      MIN_IMPEDANCE          <no rule>             50.000000
      MAX_IMPEDANCE          <no rule>             150.000000
      SHIELD_NET             <no rule>             OFF
      SHIELD_GAP             <no rule>             200.000000
      MATCH_LENGTH_TOLERANCE <no rule>             200.000000
      MATCH_LENGTH          <no rule>             OFF
      AGGRESSOR             <no rule>             OFF

NET CLASS DIFFERENCES
---------------------
OLD DESIGN NEW DESIGN

ADDED CLASS NETS
---------------------------------

REMOVED CLASS NETS
---------------------------------

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